The clock signal is essential when designing sequential circuits, the following two code examples demonstrate how to produce a clock signal for your FPGA projects. These modules could also be used to produce square wave oscillations for other purposes such as audio tones.
module Clk_Signal (clock); // Verilog 1995
parameter delay = 5;
clock = 0;
forever #delay clock = ~clock;
module Clk_Signal #(parameter delay = 5) (output reg clock); // V2001
initial forever #delay clock = ~clock;